1. Field of the Invention
The present invention relates generally to data transmission. More particularly, the present invention relates to reception of data transmissions.
2. Background Art
Clock and data recovery (CDR) circuitry may be used to extract both data and a clock from a transmitted datastream, thereby eliminating reliance on a separate clock signal that would otherwise be transmitted substantially alongside the datastream and would typically require an additional and relatively expensive transmission path. In particular, digital CDRs are widely used for their flexibility and simplicity.
However, conventional digital CDRs typically exhibit an inherent disadvantage with respect to high latency because their phase errors and loop parameters are processed in a digital domain after significant pre-processing, such as de-serialization, has been performed on an input data stream. This high latency attribute detrimentally decreases a high frequency jitter tolerance for conventional digital CDRs.
For example, a loop bandwidth for a conventional digital CDR needs to be increased to accurately track jitter of higher frequency input datastreams. However, increasing loop bandwidth without sealing down overall latency may result in unstable loop behavior and degradation in high frequency jitter tolerance. Thus, for jitter tolerance to remain substantially constant as input frequencies increase, an overall latency of the conventional digital CDR should scale down accordingly in order to allow for a commensurate increase in loop bandwidth. Unfortunately, decreasing latency of a conventional digital CDR often results in CDR timing violations due to a higher susceptibility to process, voltage and temperature variations, and can typically only be done at the cost of reduced functionality and features. Thus, reliably scaling overall latency of a conventional digital CDR with input datastream frequency becomes almost insurmountably difficult to accomplish as data rates increase, particularly for 10 Gbps input datastreams or higher.
Accordingly, there is a need to overcome the drawbacks and deficiencies in the art by providing a low latency high bandwidth CDR architecture such that its overall latency can more easily scale with high frequency input datastreams.